The present invention relates to a semiconductor device, and in particular, relates to a technique effective to be applied to a semiconductor device having semiconductor elements formed in semiconductor layers with different thicknesses.
Recently, in a mobile communication device (a mobile phone), to handle transmission and reception signals compliant with a plurality of different frequency bands and different modulation systems, one antenna is shared to transmit and receive these transmission and reception signals and connection with the antenna is switched by an antenna switching circuit. This antenna switching circuit may include an metal-insulator-semiconductor field effect transistor (MISFET) formed over an silicon on insulator (SOI) substrate.
Patent Document 1 (Japanese Patent Laid-Open No. 2008-186978) discloses a technique for manufacturing a semiconductor device to control occurrence of variation in a thickness of a nitride film near a trench, by etching when deeply digging the trench in a depth of perfect isolation to control variation in an element isolation film. Specifically, a manufacturing method of a semiconductor device having the following steps is disclosed. This manufacturing method of a semiconductor device has the steps of (a) forming a plurality of trenches [17] in a depth of partial isolation on an SOI substrate [11] with a nitride film [13] formed on its upper surface, and (b) forming an inner wall oxide film [19] in an extremely thin film state by oxidizing an inner wall of each trench [17]. Further, it has the steps of (c) forming a resist [21] over the SOI substrate [11] by exposing a specific trench [17a] among the trenches [17] and also filling the rest of the trenches [17b], and (d) deeply digging the specific trench [17a] in a depth of perfect isolation by etching a bottom portion of the specific trench [17a] using the resist [21] as a mask (refer to FIGS. 3 and 4).
Patent Document 2 (Japanese Patent Laid-Open No. 2001-339071) discloses a technique for forming a perfectly isolated portion [23] reaching an upper surface of an insulating layer [3] on an element isolation insulating film [5] of an SOI substrate [1] below a power wiring [21] (refer to FIG. 2).
Patent Document 3 (Japanese Patent Laid-Open No. 2009-170590) discloses a technique for accurate element isolation between a plurality of types of transistors, in a semiconductor device having the plurality of types of transistors formed in SOI layers with different thicknesses. Specifically, this document discloses a semiconductor device in which the SOI layer [3] has a thick film SOI region [101] and a thin film SOI region [102], an upper layer portion of the thick film SOI region [101] is formed with an epitaxial SOI layer, and an SOI film thickness [t1] of the thick film SOI region [101] is thicker than an SOI film thickness [t2] of the thin film SOI region [102] by a film thickness of this epitaxial SOI layer. In addition, a space between the thick film SOI region [101] and the thin film SOI region [102] is element-isolated by a perfectly isolated oxide film [10f], and a space between adjacent transistors is element-isolated by a partially isolated oxide film [10p] within the thick film SOI region [101] and within the thin film SOI region [102]. This document discloses a semiconductor device in which upper surfaces of the perfectly isolated oxide film [10f] and the partially isolated oxide film [10p] are formed higher than the upper surface of the SOI layer [3] in the thick film SOI region [101] and the thin film SOI region [102] (refer to FIGS. 1 and 5).
Patent Document 4 (Japanese Patent Laid-Open No. 2007-150360) discloses a technique related to a semiconductor device having an SOI structure. In addition, the paragraph [0068], with reference to FIG. 26, discloses a step of exposing a surface of an embedded oxide film [2] by performing silicon etching on an SOI layer [3] using a resist [49] as a mask to remove the SOI layer [3] not having the resist [49] formed in its upper portion and including the SOI layer [3] below a central portion of a bottom surface of a partial trench [44A]. Further, the paragraph [0069], with reference to FIG. 27, discloses a step of forming a structure having a partial oxide film [31] (and an SOI layer [3] which is below the partial oxide film [31]) and an oxide film [33] (and an SOI layer [3] which is below the partial oxide film [33]) selectively formed by depositing an oxide film and polishing it partway of a nitride film [42] by a CMP process in a technique similar to normal trench isolation, and then, by removing the nitride film [42] and the oxide film [41].
Patent Document 5 (Japanese Patent Laid-Open No. 2001-351995) discloses a semiconductor device in which an element isolation insulating film [16] is formed instead of the element isolation insulating film [5] having a structure shown in FIG. 13 at the boundary portion between a memory cell array portion and a low-voltage logic circuit portion. This element isolation insulating film [16] has a perfectly isolated portion [40] reaching an upper surface of a BOX layer [3] in a part of a bottom surface (refer to FIG. 15).
In this section, insides of the [parenthesis] denote reference numerals described in each Patent Document, and the drawing numbers denote the drawing numbers described in each Patent Document.